Insulated gate field effect semiconductor device and forming method thereof

ABSTRACT

In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, by existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to an insulated gate field effectsemiconductor device using a thin film semiconductor (hereinafterreferred to as a TFT) and a method for forming the insulated gate fieldeffect semiconductor device, and particularly to a gate electrode and amethod for forming the gate electrode.

[0003] 2. Description of Related Art

[0004] A self-alignment type of structure has been known as aconventional TFT structure. In this structure, impurity material whichprovides one conductivity type is doped by an ion implantation method orthe like using a gate electrode portion as a mask to form source/drainregions.

[0005]FIGS. 1A and 1B show a representative structure of thisself-alignment structure of a TFT. In FIG. 1A, the structure includes aninsulating substrate 21 of glass or the like, a thin film semiconductorlayer 22 in which a source region 25, a channel forming region 27 and adrain region 26 are formed, a gate insulating film 23 and a gateelectrode 24. Also, electrodes, layer insulating films, wirings, etc.which are well known but are not shown in FIG. 1A, are also formed inthis structure.

[0006] In FIG. 1A, the semiconductor layer 22 is formed of amorphoussilicon or crystallized amorphous silicon. The source region 25 and thedrain region 26 are doped with phosphorus to form N-type regions.Accordingly, the TFT as shown in FIG. 1A is an N-channel type TFT. Thegate insulating film 23 is formed of silicon oxide (SiO₂), and the gateelectrode 24 is formed of a silicon film which is doped with a largeamount of phosphorus in order to reduce the resistance of the gateelectrode 24.

[0007] The TFT shown in FIG. 1A is formed as follows. The amorphoussilicon semiconductor layer 22 is first formed on the substrate 21 by avapor phase method. Thereafter, the amorphous silicon semiconductorlayer 22 is heated or irradiated with a laser beam in order tocrystallize it, whereby the amorphous silicon semiconductor layer istransformed to crystallized silicon.

[0008] Subsequently, an oxidized silicon film serving as the gateinsulating film 23 is formed by a sputtering method or the like and asilicon film doped with phosphorus, serving as the gate electrode 24, isformed by a vapor phase method or the like. Thereafter the gateinsulating film 23 and the gate electrode 24 are formed in a patterningprocess to obtain an intermediate product having the shape shown in FIG.1A. Subsequently, implantation (introduction) of phosphorus ions(hereinafter referred to as “ion implantation”) is performed using thegate electrode 24 as a mask to form the source region 25 and the drainregion 26 in a self-alignment structure. In this case, the channelforming region 27 is automatically formed.

[0009] Thereafter, through heat treatment, activation of the introducedphosphorus impurity and scratch of the semiconductor layer 22 in the ionimplantation process are annealed. In this heat treatment, the gateelectrode 24 formed of amorphous silicon is crystallized.

[0010] In this case, the following problem occurs.

[0011] In the heat treatment after the ion implantation process, thephosphorus diffuses from the gate electrode 24 and penetrates throughthe gate insulating film 23 to the channel forming region 27, asindicated by arrows 28 of FIG. 1B, so that the channel forming region 27becomes an N-type region. As a result, the channel forming region doesnot function effectively, and the characteristic of the TFTdeteriorates.

[0012] In order to solve the above problem, the following methods (a) to(d) may be adopted:

[0013] (a) Adoption of a doping method which requires no heat treatment,

[0014] (b) Lowering the heat treatment temperature and shortening theheat treatment time,

[0015] (c) Lowering the concentration of introduced phosphorus ions intothe gate electrode 24, and

[0016] (d) Use of a metal material requiring no ion implantation for thegate electrode.

[0017] The method (a) is not realistic because the doping system itselfmust be altered. That is, those devices and forming methods which arepresently used cannot be utilized.

[0018] The method (b) cannot obtain various effects, such as theimprovement of interface characteristics at the interface between thechannel forming region 27 and the gate insulating film 23 which areobtained by heat treatment, the restoration of damage of thesemiconductor layer 22 which occurs in the ion implantation process,etc., and thus does not basically solve the problem. In practical use,as a compromise, a heat treatment condition is set in a suitablepermissible range in consideration of the treatment temperature andtreatment time in the heat treatment process and the degree of diffusionof the impurities into the channel forming region.

[0019] The method (c) necessarily causes the resistance of the gateelectrode to be increased, and this causes an increase in wiringresistance and cannot obtain the characteristics of the TFT.

[0020] In the method (d), the heat tolerance temperature of the metalmaterial of the gate electrode 24 is an important factor in the heattreatment process after ion implantation and a subsequent protectionfilm forming process. Therefore, the heat treatment temperature isrestricted. Further, there is a problem in that although the gateelectrode is not melted, the metal material of the gate electrode 24diffuses into the channel forming region 27.

[0021] The above problems occur similarly for both N-channel type Tatsand P-channel type TFTs, and are not dependent on elements introduced byion implantation.

SUMMARY OF THE INVENTION

[0022] An object of the present invention is to provide a TFT structureand a forming method thereof in which introduced ions are prevented frompenetrating through a gate insulating film 23 and diffusing into achannel forming region 27 in a heat treatment process after ionimplantation during manufacture of a TFT having a self-alignmentstructure as shown in FIG. 1A.

[0023] In order to attain the above object, according to a first aspectof the present invention, an insulated gate field effect semiconductordevice is characterized in that the concentration of impurities whichprovides one conductivity type in a gate electrode formed of asemiconductor material is set to be low in one region of the gateelectrode which is in contact with a gate insulating film, and set to behigh in the other region.

[0024] According to the first aspect of the present invention, theconcentration of impurities which provides one conductivity type in thegate electrode is set to be low at one side of the gate electrode whichis in contact with the gate insulating film, and set to be high at theopposite side of the gate electrode to the gate insulating film.Therefore, the amount of impurities which penetrate from the gateelectrode through the gate insulating film in a TFT forming process canbe reduced. The following structure can be provided to realize astructure according to the first aspect of the invention.

[0025] In the following description, the construction of each part ofFIG. 2 is the same as the construction shown in FIG. 1A, except for thestructure of the gate electrode 24.

[0026] In the structure of the TFT as shown in FIG. 2, the gateelectrode 24 formed of the semiconductor layer is so designed that theimpurity providing one conductivity type is contained at a lowconcentration at one side 31 of the gate electrode 24 which is incontact with the gate insulating film 23, and in high concentration atthe other (opposite) side 32 of the gate electrode 24 which is not incontact with the gate insulating film 23.

[0027] The structure of TFT as shown in FIG. 2 may be realized by amethod wherein the impurity which provides one conductivity type isgradually doped into the gate electrode 24 from starting of filmformation of the gate electrode 24 in accordance with the progress ofthe film formation of the gate electrode 24, or by a method wherein thegate electrode is made a multi-layered structure and the respectivelayers of the multi-layered structure are successively formed one by onewhile varying the concentration of the impurity which provides oneconductivity type.

[0028] Accordingly, the former method provides a gate electrode having acontinuously-variable impurity concentration distribution, and thelatter method provides a gate electrode having a stepwise-variableimpurity concentration distribution.

[0029] According to a second aspect of the present invention, theinsulated gate field effect semiconductor device is characterized inthat a gate electrode of semiconductor material having a double-layerstructure is provided, and an impurity which provides one conductivitytype is contained in low concentration in one layer of the gateelectrode which is in contact with a gate insulating film and in highconcentration in the other layer of the gate electrode which is not incontact with the gate insulating film.

[0030] The second aspect of the present invention has one structurewhich makes concrete the structure of the first aspect of the inventiondescribed above. That is, in the structure shown in FIG. 2, the gateelectrode 24 is designed in a double layer structure, and the layer(arranged in a portion represented by the number 31) at one side of thegate electrode 24 which is in contact with the gate insulating film 23is designed to contain a low concentration of an impurity which providesone conductivity type while the layer (arranged in a portion representedby the number 32) at the other side of the gate electrode 23 which isopposite to the gate insulating film 23 is designed to contain a highconcentration of the impurity which provides one conductivity type.

[0031] According to a third aspect of the present invention, theinsulated gate field effect semiconductor device is characterized inthat a gate electrode of a multi-layer structure which is formed ofsemiconductor material is provided, and the impurity which provides oneconductivity type is contained in low concentration in a layer of thegate electrode which is in contact with a gate insulating film, and inhigh concentration in the other layers of the gate electrode which arenot in contact with the gate insulating film.

[0032] The third aspect of the present invention corresponds to thestructure obtained by making the gate electrode of the first aspect ofthe invention a multi-layer structure. Further, when the number oflayers is limited to two, the structure corresponds to the structure ofthe second aspect of the invention.

[0033] A fourth aspect of the present invention relates to a formingmethod of an insulated field effect semiconductor device having a gateelectrode formed of a multi-layered semiconductor layer, and ischaracterized by comprising the steps of forming on a gate insulatingfilm a first semiconductor layer which is substantially intrinsic, thenforming a second semiconductor layer while doping an impurity whichprovides one conductivity type onto the first semiconductor layer.

[0034] The fourth aspect of the present invention relates to a formingmethod when realizing the third aspect of the invention. That is, thefourth aspect of the invention is characterized in that, for theformation of the gate electrode, the first layer which is in contactwith the gate insulating film is formed as a substantially intrinsicsemiconductor layer, and the impurity for providing one conductivitytype is doped when the second layer is formed on the first layer.

[0035] With the above construction, when the source/drain regions areformed in the ion implantation process and the subsequent heat treatmentprocess, the first layer (corresponding to a portion 31 in FIG. 2, forexample) serves as a buffer layer, and the impurity for providing oneconductivity type which is doped in the second layer (corresponding to aportion 32 in FIG. 2, for example) can be suppressed or practicallyprevented from penetrating through the gate insulating film anddiffusing into the channel forming region. The impurity for providingone conductivity type is diffused from the second layer into the firstlayer. In this case, it is desired that the first layer is preferablydesigned to be of one conductivity type.

[0036] Further, by doping the second layer with a large amount ofimpurity for providing one conductivity type, the electrical resistanceof the gate electrode itself can be sufficiently reduced.

[0037] A fifth aspect of the present invention relates to a formingmethod of an insulated gate field effect semiconductor device having agate electrode formed of a multi-layer semiconductor layer, and ischaracterized by comprising the steps of forming a first semiconductoron a gate insulating film while doping an impurity for providing oneconductivity type at low concentration, and forming a secondsemiconductor layer on the first semiconductor layer while doping theimpurity at a higher concentration than that in forming of the firstsemiconductor layer.

[0038] The fifth aspect of the present invention is a modification ofthe fourth aspect of the invention, and the first layer which is incontact with the gate electrode is doped with the impurity for providingone conductivity type in such an amount that no practical problemoccurs. Of course, the doping amount of the impurity into the firstlayer must be determined in consideration of the fact that the impuritypenetrates through the gate insulating film and diffuses into thechannel forming region in the ion implantation and heat treatmentprocesses to form the source/drain regions. That is, the doping amountof the impurity into the first layer must be reduced to such a valuethat diffusion of the impurity is insignificant.

[0039] A sixth aspect of the present invention relates to a formingmethod of an insulated gate field effect semiconductor device having agate electrode formed of semiconductor material, and is characterized bya step of forming a gate electrode on a gate insulating film whiledoping an impurity for providing one conductivity type, wherein, in thefilm forming step as described above, doping of the impurity is notperformed at the time of film formation initiating, then the dopingamount is continuously increased or increased stepwise in accordancewith the progress of the film formation.

[0040] According to the sixth aspect of the present invention, in thegate electrode having a single-layer structure, doping is not performedat the time of film formation initiating. Thereafter, at the stage wherefilm formation has proceeded, the film formation is performed whiledoping the impurity for providing one conductivity type. Accordingly, asshown in the embodiment of FIG. 2, the doping concentration of the layer(region) 31 is low and the doping concentration of the layer (region) 32is high after the ion implantation and heat treatment processes.

[0041] A seventh aspect of the present invention relates to a formingmethod of an insulated gate field effect semiconductor device having agate electrode formed of a semiconductor material, and is characterizedby comprising a step of forming a gate electrode on a gate insulatingfilm while doping an impurity for providing one conductivity type,wherein in the above film forming process of the gate electrode, thedoping of the impurity at a low concentration is performed at startingof film formation, and the doping concentration is increasedcontinuously or stepwise in accordance with the progress of the filmformation.

[0042] The seventh aspect of the invention corresponds to a case wherethe impurity for providing one conductivity type is doped at a lowconcentration into the region which is in contact with the gateinsulating film (corresponds to the region 31 in FIG. 2) in the sixthaspect of the invention. In the seventh aspect of the invention, thedoping amount of the impurity to be doped at the time of film formationinitiating must be determined in the ion implantation and heat treatmentprocesses so that the doped impurity is prevented from penetratingthrough the gate insulating film and diffusing into the channel formingregion.

[0043] According to this invention, a non-doped semiconductor or lowconcentration impurity doped semiconductor is formed at the one side ofthe gate electrode which is in contact with the gate insulating film,and a high concentration impurity doped semiconductor is formed on theabove semiconductor. Accordingly, when ion implantation is performedusing the gate electrode as a mask to form the source/drain regions, theimpurity for providing one conductivity type which is doped in the gateelectrode is prevented from penetrating from the gate electrode throughthe gate insulating film and diffusing to the outside. In addition, thegate electrode can be designed to have a low resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044]FIGS. 1A and 1B show a conventional basic structure of a TFT;

[0045]FIG. 2 shows a basic structure of a TFT of an embodiment of thisinvention;

[0046]FIG. 3 shows a basic structure of a TFT of another embodiment ofthis invention;

[0047]FIG. 4 shows impurity concentration (calculated value) at theinterface between a channel forming region and a gate insulating filmwith variation of thickness of silicon film which is not doped(non-doped silicon film) in the film formation process in theembodiment; and

[0048]FIG. 5 shows a basic structure of a TFT of another embodiment ofthis invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Preferred embodiments according to the present invention will bedescribed below.

Embodiment 1

[0050] The following describes a preferred embodiment utilized in thepresent invention.

[0051] The basic construction of this embodiment of TFT (Thin FilmTransistor) is shown in FIG. 3. In FIG. 3, reference numeral 11represents a glass substrate, reference numeral 12 represents asemiconductor layer (1500 Å in thickness) of crystalline silicon,reference numeral 13 represents a silicon oxide film (1000 Å inthickness) serving as a gate insulating film, reference numeral 14represents a non-doped silicon semiconductor layer constituting a gateelectrode, and reference numeral 15 represents a silicon semiconductorlayer (2000 Å in thickness) doped with a high concentration ofphosphorus, serving as the gate electrode. The doping concentration ofthe phosphorus ions into the silicon semiconductor layer 15 is1×10²¹/cm³. Further, reference numeral 16 is a source region, 17 is achannel forming region and 18 is a drain region.

[0052] In this embodiment, in the construction described above, thephosphorus concentration at the interface between the channel formingregion 17 and the gate insulating film 13 is calculated in accordancewith a five stage variation of the thickness of the non-doped siliconsemiconductor layer 14, that is, 0 Å (a state where non-doped siliconsemiconductor layer 14 does not exist), 100 Å, 200 Å, 300 Å and 400 Å.

[0053] That is, by examining the phosphorus concentration at theinterface between the channel forming region 17 and the gate insulatingfilm 13, the amount of phosphorus diffused from the siliconsemiconductor layer 15 to the channel forming region 17 can be known.From this calculation, the effect of the non-doped silicon semiconductorlayer 14 can be effectively determined.

Forming Method of TFT

[0054] First, the forming method of the TFT of the embodiment shown inFIG. 3 will be hereinafter described.

[0055] First, the amorphous silicon semiconductor layer 12 is formed(deposited) at a thickness of 1000 Å on the glass substrate 11 by a wellknown low pressure CVD (Chemical Vapor Deposition) method. The formationconditions are as follows. Pressure 0.5 Torr Temperature 520° C. Filmforming gas SiH₄ 200 sccm

[0056] Subsequently, the amorphous silicon semiconductor layer 12 isheated to crystallize it. The crystallization conditions are as follows.Pressure atmospheric pressure Temperature 600° C. Time 48 hoursAtmosphere N₂

[0057] Subsequently, the silicon oxide film (SiO₂) serving as the gateinsulating film is formed at a thickness of 1000 Å on the amorphoussilicon semiconductor layer 12 by a magnetron sputtering method. Theformation conditions are as follows. RF power (13.56 MHz) 400 W Pressure0.5 Pa Atmosphere (sputter gas) O₂ Substrate temperature 150° C.

[0058] Subsequently, the non-doped silicon semiconductor layer 14 whichis the first semiconductor layer serving as the gate electrode is formedto a desired thickness on the gate insulating film 13 by the lowpressure CVD method. The formation conditions are as follows, Filmforming temperature 640° C. Film forming pressure 0.5 Torr Film forminggas SiH₄ 200 sccm

[0059] Next, the silicon semiconductor layer 15 doped with highconcentration phosphorus which is the second semiconductor layer servingas the gate electrode is formed on the non-doped silicon semiconductorlayer 14 by the low pressure CVD method. The formation conditions are asfollows. Film forming temperature 600° C. Film forming pressure 0.5 TorrFilm forming gas PH₃/SiH₄ = 0.5% 200 sccm

[0060] Through the above film formation, the silicon semiconductor layer15 doped with phosphorus of 1×10²¹/cm³ is formed.

[0061] Subsequently, ion implantation is performed to form the sourceregion 16, the drain region 18 and the channel forming region 17 in aself-alignment structure. In this process, the source region 16 and thedrain region 18 are doped with phosphorus to about 1.7×10¹⁹/cm³.

[0062] After the ion implantation, the heat treatment is performed toactive phosphorus ions and the annealing of scratches due to the ionimplantation. The heat treatment conditions are as follows. Treatmenttemperature 600° C. Treatment time 24 hours Treatment atmosphere N₂ gasTreatment pressure Atmospheric pressure

[0063] If necessary, wirings for the source electrode, the drainelectrode, the gate electrode, etc. are formed (not shown).

[0064] In this embodiment, the gate electrode is designed in adouble-layer structure, however, it may be designed in a multi-layerstructure. In this case, it is effective to vary the dopingconcentration stepwise from the layer which is in contact with the gateinsulating film.

Estimation Method

[0065]FIG. 4 is a graph showing calculation values of the concentrationof phosphorus at the interface between the channel forming region 17 andthe gate insulating film 13 when the thickness of the non-doped siliconsemiconductor layer 14 is varied every 100 Å from 0 Å to 400 Å. Thecalculation method is as follows. On the basis of the phosphorusconcentration in the silicon semiconductor layer 15 whose phosphorusconcentration is known, the diffusion amount of phosphorus into thenon-doped silicon semiconductor layer 14 and the gate insulating film 13at a temperature of 600° C. is calculated to thereby determine whatconcentration of phosphorus penetrating through the gate insulating film13 exists in the vicinity of the interface between the channel formingregion 17 and the gate insulating film 13 through 24 hour heat treatmentat 600° C.

Estimation Result

[0066] As shown in FIG. 4, by providing the non-doped siliconsemiconductor layer 14 at the gate electrode and increasing thethickness of the layer 14, the phosphorus concentration in the vicinityof the interface between the channel forming region 17 and the gateinsulating film 13 can be decreased. In particular, by setting thethickness of the non-doped silicon semiconductor layer 14 at 400 Å ormore, the phosphorus concentration in the vicinity of the interfacebetween the channel forming region 17 and the gate insulating film 13can be decreased to about 1×10¹⁰/cm³ even when phosphorus concentrationof about 7×10²¹/cm³ is doped into the upper layer of the gate electrode.Accordingly, although abnormal diffusion of phosphorus due to the heattreatment and contamination of phosphorus in the forming process shouldbe considered, these effects can be sufficiently suppressed.

[0067] In FIG. 4, the heat treatment temperature is 600° C., asdescribed above. However, the present invention can be applied at theheat treatment temperature of 600 to 1000° C. In this temperature range,for example, concentration of the layer (region) 31 in which is incontact with the gate insulating film is 1×10²⁰/cm³ to 1×10¹¹/cm³,according to our calculation. Accordingly, when the layer 31 in FIG. 2has a desired concentration within this concentration range inaccordance with the heat treatment temperature, the resistance of thegate electrode is reduced, and the adverse effect on the channel formingregion due to diffusion of the impurity in the ion implantation processand the subsequent heat treatment process for annealing can beprevented.

Embodiment 2

[0068] In this embodiment, the gate electrode comprising the layers 14and 15 in the TFT of the embodiment 1 is designed as a monolayer siliconfilm. This embodiment is different from the first embodiment only in theconstruction of the gate electrode and the film forming method thereof.Accordingly, in this embodiment the film forming method of the gateelectrode will be described.

[0069]FIG. 5 shows the basic construction of the TFT of anotherembodiment. The portions other than the gate electrode 51 are the sameas shown in FIG. 3, and the same elements are represented by the samereference numbers as in FIG. 3.

[0070] In the TFT as shown in FIG. 5, the gate electrode 51 is formed ofsilicon semiconductor, and in order to reduce the resistance thereof,phosphorus is doped at varied concentrations.

[0071] In this embodiment, the thickness of the gate electrode 51 is2000 Å. Phosphorus is not doped into a lower layer portion 52 of 400 Åthickness in the film forming process, and a high concentration ofphosphorous (1×10²¹/cm³) is doped into an upper layer portion 53 of 1600Å thickness in the film forming process.

[0072] The film forming method of the gate electrode is as follows. Whenthe silicon film serving as the gate electrode 51 is formed by a vaporphase method such as the LPCVD (Low Pressure Chemical Vapor Deposition)method or the like, film formation is started without introducingphosphine (PH₃) serving as a raw material for doping phosphorus into areaction chamber to form the silicon film 52 of 400 Å thickness.Thereafter, phosphine is introduced into a reaction chamber at a pointduring the film forming process so as to subsequently form the siliconfilm 53 of 1600 Å thickness which is doped with phosphorus.

[0073] This process further has process of introducing reactive gascontaining an impurity for providing one conductivity type into areaction chamber in comparison with the conventional film formingprocess, and thus it is industrially effective.

[0074] Further, in the above construction, the following concentrationgradation method may be used in place of the introduction of phosphineat a point during the film forming process. That is, phosphine is notintroduced at the starting of the film forming process, but it isintroduced by gradually increasing the amount thereof during the filmforming process. By this method, the gate electrode can be so designedthat phosphorus concentration is low at the interface between the gateelectrode 51 and the gate insulating film 13 and high at the surface ofthe gate electrode 51 opposite to the interface to make the resistanceat this place low.

Other Structures Using this Invention

[0075] Other structures using this invention are described below.

[0076] In the above, an N-channel type of TFT having the basicconstruction using this invention is shown. However, this invention maybe applied to a TFT which is formed by performing ion implantation of animpurity for providing one conductivity type into a semiconductor usinga gate electrode as a mask and performing heat treatment to form sourceand drain regions and also a channel forming region in a self-alignmentstructure. Further, the kind of semiconductor is not limited to silicon.In addition, crystallization of the semiconductor is not limited, andamorphous, microcrystal, polycrystal or the like is used in the presentinvention.

[0077] Further, this invention may be used as a construction or processthereof for preventing the diffusion of the impurity from the gateelectrode into the channel forming region for TFTs which are formed bymethods other than those using ion implantation.

[0078] According to this invention, in the TFT obtained by doping theimpurity for providing one conductivity type through ion implantation toform the source region and the drain region in a self-alignmentstructure, the gate electrode is designed in the double layer structurewherein the silicon film doped with no impurity and the silicon filmdoped with high concentration impurity are laminated to each other onthe gate insulating film side in that order. Therefore, the resistanceof the gate electrode itself is reduced, and the adverse effect on thechannel forming region due to diffusion of the impurity in the ionimplantation process and the subsequent heat treatment process can beprevented.

[0079] Further, in the TFT using crystalline silicon (generally known aspolysilicon), there occurs a problem in that the absolute value of thethreshold value thereof is high. In order to solve this problem, it iseffective to decrease the thickness of the gate insulating film.However, as described above, when the semiconductor material is used forthe gate electrode, the existence of the impurity penetrating throughthe gate insulating film in the heat treatment process induces acritical problem, and thus it is difficult to decrease the thickness ofthe gate electrode.

[0080] However, according to this invention, the problem of penetrationof the impurity through the gate insulating film can be solved bymodifying the structure of the gate electrode, and thus the thickness ofthe gate insulating film can be decreased within the permissible rangeof conditions for pressure-proofing the gate insulating film, stepcoverage in the film forming process, film forming distribution, etc.Accordingly, a TFT having a thin gate insulating film and thus a desiredlow threshold value can be formed.

What is claimed is:
 1. An insulated gate field effect semiconductordevice comprising: a semiconductor film comprising silicon on aninsulating surface; and a gate electrode added with impurities forproviding one conductivity type and located adjacent to saidsemiconductor film with a gate insulating film interposed therebetween,wherein said gate electrode has a double-layer structure comprising afirst layer and a second layer located on said first layer, said firstlayer comprising silicon, and wherein a first concentration of saidimpurities in said first layer is 1×10¹¹ to 1×10²⁰/cm³.
 2. An insulatedgate field effect semiconductor device according to claim 1 wherein saidsemiconductor device is selected from an N-channel type TFT and aP-channel type TFT.
 3. An insulated gate field effect semiconductordevice according to claim 2 wherein said semiconductor film has acrystallinity selected from amorphous, microcrystal and polycrystal. 4.An insulated gate field effect semiconductor device comprising: asemiconductor film comprising silicon on an insulating surface; and agate electrode added with impurities for providing one conductivity typeand located adjacent to said semiconductor film with a gate insulatingfilm interposed therebetween, wherein said gate electrode has amulti-layer structure comprising at least a first layer and a secondlayer, said first layer comprising silicon and being in contact withsaid gate insulating film, and wherein a concentration of saidimpurities in said first layer is 1×10¹¹ to 1×10²⁰/cm³.
 5. An insulatedgate field effect semiconductor device according to claim 4 wherein saidsemiconductor device is selected from an N-channel type TFT and aP-channel type TFT.
 6. An insulated gate field effect semiconductordevice according to claim 4 wherein said semiconductor film has acrystallinity selected from amorphous, microcrystal and polycrystal. 7.An insulated gate field effect semiconductor device comprising: asemiconductor film comprising silicon on an insulating surface; and agate electrode located adjacent to said semiconductor film with a gateinsulating film interposed therebetween, wherein said gate electrode hasat least a first layer comprising silicon and a second layer located onsaid first layer, said first layer added with no impurities forproviding one conductivity type and said second layer added with saidimpurities.
 8. An insulated gate field effect semiconductor deviceaccording to claim 7 wherein said semiconductor device is selected froman N-channel type TFT and a P-channel type TFT.
 9. An insulated gatefield effect semiconductor device according to claim 7 wherein saidsemiconductor film has a crystallinity selected from amorphous,microcrystal and polycrystal.
 10. An insulated gate field effectsemiconductor device comprising: a semiconductor film comprising siliconon an insulating surface; and a gate electrode located adjacent to saidsemiconductor film with a gate insulating film interposed therebetween,wherein said gate electrode has a multi-layer structure comprising atleast a first layer and a second layer, said first layer being incontact with said gate insulating film and comprising silicon, saidsecond layer added with impurities for providing one conductivity type,and wherein a first concentration of said impurities in said first layeris 1×10¹¹ to 1×10²⁰/cm³.
 11. An insulated gate field effectsemiconductor device according to claim 10 wherein said semiconductordevice is selected from an N-channel type TFT and a P-channel type TFT.12. An insulated gate field effect semiconductor device according toclaim 10 wherein said semiconductor film has a crystallinity selectedfrom amorphous, microcrystal and polycrystal.
 13. An insulated gatefield effect semiconductor device comprising: a semiconductor filmcomprising silicon on an insulating surface; and a gate electrode addedwith impurities for providing one conductivity type and located adjacentto said semiconductor film with a gate insulating film interposedtherebetween, wherein said gate electrode comprises a region in contactwith said gate insulating film, said region comprising silicon, andwherein a concentration of said impurities in said gate electrode iscontinuously or stepwise decreased toward said gate insulating film andsaid concentration is 1×10¹¹ to 1×10²⁰/cm³ in said region.
 14. Aninsulated gate field effect semiconductor device according to claim 13wherein said semiconductor device is selected from an N-channel type TFTand a P-channel type TFT.
 15. An insulated gate field effectsemiconductor device according to claim 13 wherein said semiconductorfilm has a crystallinity selected from amorphous, microcrystal andpolycrystal.
 16. An insulated gate field effect semiconductor devicecomprising: a semiconductor film comprising silicon on an insulatingsurface; and a gate electrode located adjacent to said semiconductorfilm with a gate insulating film interposed therebetween, wherein saidgate electrode has at least a first layer comprising silicon and asecond layer located on said first layer, said first layer added with noimpurities for providing one conductivity type and said second layeradded with said impurities, and wherein a concentration of saidimpurities in said gate electrode is continuously or stepwise decreasedtoward said gate insulating film.
 17. An insulated gate field effectsemiconductor device according to claim 16 wherein said semiconductordevice is selected from an N-channel type TFT and a P-channel type TFT.18. An insulated gate field effect semiconductor device according toclaim 16 wherein said semiconductor film has a crystallinity selectedfrom amorphous, microcrystal and polycrystal.
 19. An insulated gatefield effect semiconductor device comprising: a semiconductor filmcomprising silicon on an insulating surface, said semiconductor filmhaving at least a source region, a drain region and a channel formingregion between said source region and said drain region; a gateinsulating film in contact with said channel forming region; and a gateelectrode in contact with said gate insulating film, said gate electrodeadded with impurities for providing one conductivity type, wherein saidgate electrode comprises a first region and a second region, said firstregion comprising silicon and being in contact with said gate insulatingfilm, and wherein a first concentration of said impurities in said firstregion is 1×10¹¹ to 1×10²⁰/cm³.
 20. An insulated gate field effectsemiconductor device according to claim 19 wherein said semiconductordevice is selected from an N-channel type TFT and a P-channel type TFT.21. An insulated gate field effect semiconductor device according toclaim 19 wherein said semiconductor film has a crystallinity selectedfrom amorphous, microcrystal and polycrystal.
 22. An insulated gatefield effect semiconductor device comprising: a semiconductor filmcomprising silicon on an insulating surface, said semiconductor filmhaving at least a source region, a drain region and a channel formingregion between said source region and said drain region; a gateinsulating film in contact with said channel forming region; and a gateelectrode in contact with said gate insulating film, said gate electrodeadded with impurities for providing one conductivity type, wherein saidgate electrode has a double-layer structure comprising a first layer anda second layer located on said first layer, said first layer comprisingsilicon, and wherein a first concentration of said impurities in saidfirst layer is 1×10¹¹ to 1×10²⁰/cm³.
 23. An insulated gate field effectsemiconductor device according to claim 22 wherein said semiconductordevice is selected from an N-channel type TFT and a P-channel type TFT.24. An insulated gate field effect semiconductor device according toclaim 22 wherein said semiconductor film has a crystallinity selectedfrom amorphous, microcrystal and polycrystal.
 25. An insulated gatefield effect semiconductor device comprising: a semiconductor filmcomprising silicon on an insulating surface, said semiconductor filmhaving at least a source region, a drain region and a channel formingregion between said source region and said drain region; a gateinsulating film in contact with said channel forming region; and a gateelectrode in contact with said gate insulating film, said gate electrodeadded with impurities for providing one conductivity type, wherein saidgate electrode has a multi-layer structure comprising at least a firstlayer and a second layer, said first layer comprising silicon and beingin contact with said gate insulating film, and wherein a concentrationof said impurities in said first layer is 1×10¹¹ to 1×10²⁰/cm³.
 26. Aninsulated gate field effect semiconductor device according to claim 25wherein said semiconductor device is selected from an N-channel type TFTand a P-channel type TFT.
 27. An insulated gate field effectsemiconductor device according to claim 25 wherein said semiconductorfilm has a crystallinity selected from amorphous, microcrystal andpolycrystal.
 28. An insulated gate field effect semiconductor devicecomprising: a semiconductor film comprising silicon on an insulatingsurface, said semiconductor film having at least a source region, adrain region and a channel forming region between said source region andsaid drain region; a gate insulating film in contact with said channelforming region; and a gate electrode in contact with said gateinsulating film, said gate electrode added with impurities for providingone conductivity type, wherein said gate electrode comprises a region incontact with said gate insulating film, said region comprising silicon,and wherein a concentration of said impurities in said gate electrode iscontinuously or stepwise decreased toward said gate insulating film andsaid concentration is 1×10¹¹ to 1×10²⁰/cm³ in said region.
 29. Aninsulated gate field effect semiconductor device according to claim 28wherein said semiconductor device is selected from an N-channel type TFTand a P-channel type TFT.
 30. An insulated gate field effectsemiconductor device according to claim 28 wherein said semiconductorfilm has a crystallinity selected from amorphous, microcrystal andpolycrystal.